Evidence

Engineering intelligence at work.

Better search decisions. Learned layout guidance. Working circuits and connected mixed-signal systems. Explore the results behind Nectrion's engineering-intelligence platform.

On record

Selected results.

What ran and what it showedTierScope

Model-guided search finds stronger engineering trade-offs

On an SG13G2 LNA, Bayesian search achieved 14.6 percent higher median Pareto hypervolume than NSGA-III at the same simulation budget. Separate SG13G2 bandgap, CTLE and two-stage op-amp cases recorded hypervolume ratios of 1.21–2.74 for Bayesian search versus the evolutionary baseline.

Simulation A/B

LNA: five seeds, 60 simulations per arm, typical corner. Other named cases: three seeds, 60 per arm. Hypervolume measures trade-off coverage at a shared reference; timings and the full campaign comparison are available with the methodology.

Wideband LNA design across architectures and corners

A multi-topology, 1–6 GHz campaign maps the gain, noise, power and linearity trade-offs of a jammer-tolerant front end. The selected 3.3 V design meets six of eight specified metrics across seven process and temperature corners on the foundry's HICUM models.

Tier 1

Schematic simulation on IHP SG13G2. Six-metric closure covers the selected 3.3 V design; the campaign also characterizes a 5 V class-AB path.

Operational amplifier closed to a commercial construct-and-verify witness

An op-amp closes end to end to an agreed commercial-tool construction and verification witness, replayable from pinned code and inputs. Internally live-validated.

Tier 3 witness

One op-amp, internally live-validated on a licensed Cadence construct-and-verify path; schematic-level commercial evidence.

SenseSoC-1: decisions coordinated at system scale

Analog circuitry, digital control, interfaces and a power budget share one typed architecture. The five-corner campaign achieved 25.65 dB worst-corner SNDR and 3.97 effective bits, meeting the 24 dB target. The system budget is 4.926 of 5.0 mW.

Tier 1

Open-tool schematic and AMS simulation. Power combines 0.426 mW simulated analog with 4.5 mW allocated to digital and interfaces.

Sky130 physical results

Layouts on the SkyWater 130 nm open process pass design-rule checks with zero violations and match their schematics in layout-versus-schematic comparison.

Tier 2

Open-tool physical checks. Extracted performance is reported per block for supported flows.

In-house electromagnetic solver against a commercial reference

A parameter-free method-of-moments and boundary-element solver for on-chip passives, compared differentially against Cadence EMX at low frequency across 22 committed geometries, with no fixture fitting. Inductance error 0.19 to 12.29 percent, median 2.62 percent. Resistance error 1.82 to 10.55 percent, median 2.94 percent. All 22 geometries are Sky130 spiral inductors on one metal stack, and they are the development set.

Solver comparison

Low-frequency solver-to-solver comparison on one process, one stackup and one structure family; the 22 geometries are the development set.

Prediction, adaptive search and experience reuse

Probabilistic circuit models predict response and uncertainty; learned risk models guide candidate and corner selection. A cross-run experience store supplies prior designs to a learned warm-start proposer and compatible observations to system planning.

Capability

Implemented optimizer and runtime paths. Compatible observations inform search and planning; proposed seeds are evaluated against the new requirements.

Evaluate placement alternatives faster before committing to expensive routing

A learned via-cost model delivered a 5.6× median placement-search speedup against router-in-loop cost evaluation in a six-fixture study. Our native spatial ranker achieved mean rank correlation of 0.79–0.81 using three to five evaluated configurations of each target design.

Layout ML

Placement: measured search runtime; DRC results vary by fixture. Ranking: four rankable designs, a 99-configuration pool, six draws; mean false-prune rate 1–5 percent. Helps choose which remaining placed candidates to route.

Replay

Explore the system behind the results.

The research foundation also includes CNN and U-Net congestion models and supervised/RL training for mirror-equivariant placement policies. Discuss the workflow, review the complete comparisons, or request a pinned evidence bundle with its specification, tool versions, candidates and verification results.

Discuss the evidence

How to read these results

Each result names the kind of evidence behind it. The kinds are ordered by how much of physical reality each has met, and they are not cumulative.

Tier 1Schematic simulation on real process models, across corners. The circuit is simulated with the foundry's device models at multiple process and temperature points. It shows what the topology and sizing can reach; it does not include layout parasitics.demonstrated

Tier 2Open-tool layout with extraction and physical checks. A layout passes design-rule and layout-versus-schematic checks, and the extracted parasitics are fed back into simulation.partial

Tier 3Commercial-tool construction and verification. A closure reproduced through the industry's commercial tools at the schematic level: construction and verification, not parasitic extraction or signoff.witness